Model checking embedded control software using OS-in-the-loop CEGAR
Verification of multitasking embedded software requires taking into account its underlying operating system w.r.t. its scheduling policy and handling of task priorities in order to achieve a higher degree of accuracy. However, such comprehensive verification of multitasking embedded software together with its underlying operating system is very costly and impractical. To reduce the verification cost while achieving the desired accuracy, we propose a variant of CEGAR, named OiL-CEGAR (OS-in-the-Loop Counterexample-Guided Abstraction Refinement), where a composition of a formal OS model and an abstracted application program is used for comprehensive verification and is successively refined using the counterexamples generated from the composition model. The refinement process utilizes the scheduling information in the counterexample, which acts as a mini-OS to check the executability of the counterexample trace on the concrete program. Our experiments using a prototype implementation of OiL-CEGAR show that OiL-CEGAR greatly improves the accuracy and efficiency of property checking in this domain. It automatically removed all false alarms and accomplished property checking within an average of 476 seconds over a set of multitasking programs, whereas model checking using existing approaches over the same set of programs either showed an accuracy of under 11.1% or was unable to finish the verification due to timeout.
Wed 13 NovDisplayed time zone: Tijuana, Baja California change
13:40 - 15:20 | Verification and Bug DetectionDemonstrations / Research Papers at Cortez 1 Chair(s): Raghavan Komondoor Indian Institute of Science, Bangalore | ||
13:40 20mTalk | Mutation Analysis for Coq Research Papers Ahmet Celik The University of Texas at Austin, Karl Palmskog University of Texas at Austin, Marinela Parovic The University of Texas at Austin, Emilio Jesús Gallego Arias MINES ParisTech, Milos Gligoric The University of Texas at Austin | ||
14:00 20mTalk | Verifying Arithmetic in Cryptographic C Programs Research Papers Jiaxiang Liu Shenzhen University, Xiaomu Shi Shenzhen University, Ming-Hsien Tsai Academia Sinica, Taiwan, Bow-Yaw Wang Academia Sinica, Bo-Yin Yang Academia Sinica Pre-print | ||
14:20 20mTalk | Model checking embedded control software using OS-in-the-loop CEGAR Research Papers Pre-print | ||
14:40 20mTalk | Get rid of inline assembly through verification-oriented lifting Research Papers Frédéric Recoules CEA LIST, Sébastien Bardin CEA LIST, Richard Bonichon CEA LIST, Laurent Mounier Université Grenoble Alpes, Marie-Laure Potet Université Grenoble Alpes DOI Pre-print | ||
15:00 10mDemonstration | VeriAbs : Verification by Abstraction and Test Generation Demonstrations Mohammad Afzal Tata Cosultancy Services, A Asia Tata Cosultancy Services, Avriti Chauhan Tata Cosultancy Services, Bharti Chimdyalwar Tata Consultancy Services, Priyanka Darke Tata Consultancy Services, Advaita Datar Tata Consultancy Services Ltd, Shrawan Kumar Tata Cosultancy Services, R Venkatesh Tata Research Development and Design Centre | ||
15:10 10mDemonstration | SGUARD: A Feature-based Clustering Tool for Effective Spreadsheet Defect Detection Demonstrations Da Li State Key Lab. for Novel Software Tech. and Dept. of Comp. Sci. and Tech., Nanjing University, Nanjing, China, Huiyan Wang State Key Lab. for Novel Software Tech. and Dept. of Comp. Sci. and Tech., Nanjing University, Nanjing, China, Chang Xu Nanjing University, Ruiqing Zhang Search Tech. Center Asia, Microsoft, Suzhou, China, Shing-Chi Cheung Department of Computer Science and Engineering, The Hong Kong University of Science and Technology, Xiaoxing Ma State Key Lab. for Novel Software Tech. and Dept. of Comp. Sci. and Tech., Nanjing University |